Performing a Timing Simulation with the Incisive Enterprise Simulator Software
The following sections demonstrate how to perform a timing simulation of a Intel® Quartus® Prime-generated Verilog Output File (.vo) Definition and the corresponding Standard Delay Format Output File (.sdo) Definition with the Cadence Incisive Enterprise Simulator (IES) software:
Note: For more information about using EDA simulators, refer to
Cadence
Incisive Enterprise Simulator Support in the
Intel® Quartus® Prime
Handbook.
If you want to perform power analysis, perform power analysis with the Power Analyzer.