Start EDA Netlist Writer Command (Processing Menu)
You access this command by pointing to
.
You can use the EDA Netlist Writer module to generate VHDL Output File (.vho) DefinitionVerilog Output File (.vo) Definition and Standard Delay Format Output File (.sdo) Definition for a design. You can compile a design and then specify different EDA tool settings and regenerate the netlist files without recompiling the design.
You can also use this command to generate the following types of files:
- Stamp model files Definition
- PartMiner edaXML-Format File (.xml) Definition
- FPGA Xchange-Format File (.fx) Definition for symbol generation in board-level verification tools
- IBIS Output File (.ibs) Definition
- HSPICE Simulation Deck File (.sp) Definition
- Script files to generate Value Change Dump File (.vcd) Definition in EDA simulation tools
Note: If you use this command after the design source
files change after compilation, the Intel® Quartus® Prime software generates the output netlist
files with the data from the last compilation.
You can also generate netlist files for use by third-party EDA tools with the IP Catalog.