LogicLock Plus Region Definition

A LogicLock® Plus region is a type of placement constraint. You can define any arbitrary region of physical resources on the target device as a LogicLock® Plus region. When you assign nodes or entities to a LogicLock® Plus region, you direct the Compiler to place those nodes or entities inside the region during fitting. A LogicLock® Plus region has a fixed size and location.

The Reserved option prevents the Fitter from placing nodes not assigned to the LogicLock® Plus region within the LogicLock® Plus region. To support team-based design, you can reserve areas of a device by creating a reserved LogicLock® Plus region without assigning nodes or entities to the LogicLock® Plus region.

LogicLock® Plus back-annotation allows you to back-annotate all nodes in a LogicLock® Plus region. Nodes back-annotated with LogicLock® Plus back-annotation are locked relative to the edges of the region. If you move a back-annotated region, its member nodes maintain their relative placement in the new location.

LogicLock® Plus regions can be nested hierarchically. If you move a parent region, child regions maintain their placement relative to their parent region.

LogicLock® Plus assignments can be exported in a Quartus® Prime Settings File (.qsf) for reuse in other designs.

You can create a LogicLock® Plus region without assigning nodes or entities to it. A LogicLock® Plus region is visible in the Chip Planner and the LogicLock® Plus Regions window until you delete it, regardless of whether any nodes are currently assigned to the LogicLock® Plus region.