ID:10191 Verilog HDL Compiler Directive warning at <location>: text macro "<name>" is undefined
CAUSE: In a Verilog Design File (.v) at the specified location, you used the specified macro by typing the (`
) character followed by the text macro name, but the macro was not previously defined with a `define
directive. This message may occur if you forgot to define the macro, or it may also occur if you were not intending to use a macro, but accidentally typed an accent grave or "back tick" character (`
).
ACTION: Define the macro, or if you were not intending to use a macro, remove the (`
) character.