ID:332197 Results limited to <number> timing edges
CAUSE: The timing edges have minimum delays greater than maximum delays, resulting in timing model optimism. This message might occur if the set_annotated_delay
or the set_timing_derate
Synopsys Design Constraints File (.sdc) commands were incorrectly used. If this occurs in the clock network and the common clock path pessimism (CCPP) removal is enabled, the CCPP will be reset to zero if the calculated CCPP is negative.
ACTION: Check your Synopsys Design Constraints File command to make sure that the set_annotated_delay
and the set_timing_derate
commands are correct.