ID:21016 ADD_PHASE_TRANSFER_REG parameter of OUTPUT_PHASE_ALIGNMENT primitive "<name>" must be set to TRUE
CAUSE: The
ADD_PHASE_TRANSFER_REG
parameter of the specified OUTPUT_PHASE_ALIGNMENT
primitive is set to an illegal value. The ADD_PHASE_TRANSFER_REG
parameter must be set to TRUE if the following conditions are met: -
bypass_input_register
is set toFALSE
and -
use_delayed_clock
is set toFALSE
and -
use_phasectrl_clock
is set toFALSE
and - the
datain[]
input signal is notVCC
orGND
.
ACTION: Check the design and make sure that the specified parameter values are not in conflict with each other.