ID:14731 Ignored Maximum Fan-Out logic option for node "<name>"
CAUSE: You turned on the
Maximum Fan-Out
logic option for the specified node and specified a fan-out limit. However, the fan-out from the node exceeds the limit you specified, and Analysis & Synthesis cannot reduce the fan-out below the specified limit. As a result, Analysis & Synthesis is ignoring the Maximum Fan-Out logic option for the specified node. This message may occur if Analysis & Synthesis cannot implement the Maximum Fan-Out logic option because the specified node or
LCELL
does not meet the following required conditions:- The node or
LCELL
cannot have the optionIgnore Maximum Fan-Out Assignments
set to On. - The node or
LCELL
cannot have the optionNetlist Optimizations
set to Never Allow. - The node or
LCELL
cannot feed itself. - The node or
LCELL
cannot use more than one output. - The node or
LCELL
's output port cannot feed ports such as clock and asynchronous clear. - The node or
LCELL
cannot be part of a carry or cascade chain.
ACTION: No action is required. To avoid receiving this message in the future, change the option Ignore Maximum Fan-Out Assignments to Off, change the option Netlist Optimizations to Default or Always Allow, or modify the design so that the fan-out from the node does not exceed the limit, or so that the specified node or LCELL
meets the conditions required for the Maximum Fan-Out logic option.