ID:10264 Verilog HDL Case Statement information at <location>: all case item expressions in this case statement are onehot
CAUSE: In a Verilog Design File (.v) , you used a case statement in which all case item expressions are onehot. That is, each case item expression is an N-bit constant with N - 1 bits set to
0
and one bit set to 1
: for example, 4'b0010
. However, the case statement does not have a full_case
attribute, or it has a full_case
attribute and a default case item. Therefore, the full_case
attribute is ignored. Without an active
full_case
attribute, Quartus Prime Integrated Synthesis cannot reduce the logic required to implement the case statement by exploiting the onehot nature of the case item expressions. In the following Verilog HDL example, the case statement has both onehot case item expressions and a full_case
attribute. As a result, Quartus Prime Integrated Synthesis can optimize this case statement.reg [3:0] sel; // sel is a onehot encoded signal
reg result, a, b, c, d;
always @ (sel or a or b or c or d) begin
case(sel) // synthesis full_case
4'b0001: result = a;
4'b0010: result = b;
4'b0100: result = c;
4'b1000: result = d;
endcase
end
The example makes the assumption that sel
is a onehot encoded variable.ACTION: If your case statement does not require a default case item (that is, if there is a case item that matches every possible value of the case expression), add a full_case
attribute to the case statement and/or remove the default case item, if it exists. If your case statement requires a default case item, do not add a full_case
attribute to your case statement. Adding the attribute would cause a mismatch between the simulated behavior of the design and the synthesized netlist.