ID:10250 Verilog HDL Declaration error at <signed type>: objects with <type name> type cannot be declared as <location>
CAUSE: In a Verilog Design File (.v) at the specified location, you declared one or more objects with the specified type. In addition, you specified the object(s) as signed
or unsigned
. However, Quartus Prime Integrated Synthesis does not allow you to specify signed
or unsigned
when declaring objects with integer
, real
, time
, or realtime
types.
ACTION: Remove the signed
or unsigned
keyword from the object declaration or change the object declaration's type.