ID:10249 Verilog HDL Declaration error at <location>: objects with <type name> type cannot be declared with a range
CAUSE: In a Verilog Design File (.v) at the specified location, you declared one or more objects with the specified type. You also specified a range in the object declaration. However, Quartus Prime Integrated Synthesis does not support ranges for objects with integer
, real
, time
, or realtime
types.
ACTION: Remove the range or modify the declared type of the object(s).