ID:10655 Verilog HDL or VHDL Synthesis Directive error at <location>: "<name>" is not a legal value for the message_level synthesis directive
CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you used the specified value for the message_level
synthesis directive. However, the specified value is not a legal value for this synthesis directive. Legal message_level
values are Level1
, Level2
, Level3
.
ACTION: Specify a legal value for the message_level
synthesis directive.