ID:13234 Verilog HDL unsupported feature error at file "<name>" line (<number>): can't synthesize pull-up or pull-down primitive
CAUSE: In a Verilog Design File (.v) at the specified location, you used a pullup
or pulldown
primitive. However, the pullup
and pulldown
gates are not supported for Quartus Prime Integrated Synthesis, because resistive pullup
and pulldown
primitives cannot be implemented in Intel FPGA devices, except as part of a tri-state driver driving a bidirectional pin.
ACTION: If you need to implement a tri-state driver driving a bidirectional pin, use a construct like the one shown in the following example:
if (enable == 1'b1)
tri_out <= my_sig;
else
tri_out <= 1'bz;
For all other cases, edit the design to use only logic value 1
and logic value 0
.