ID:13377 Verilog HDL Function Declaration error at <location>: must not use output or inout ports in Verilog HDL functions
CAUSE: In a Function Declaration at the specified location in a Verilog Design File (.v), you declared a function that has an output
or inout
port. However, Verilog HDL functions must have only input
ports. You must not specify an output
or inout
port for a Verilog HDL function, because the function name itself is the name of the output port.
ACTION: Remove the
output
or inout
port argument, so the Function Declaration shows only input
ports, as shown in the following example, which implements a two-input AND
function:function my_and_func;
input a;
input b;
begin
my_and_func = a & b;
end
endfunction // my_func
To use this function in a Verilog HDL module, you would use the following syntax: assign out = my_func(in1, in2);