ID:13354 Verilog HDL User-Defined Primitive (UDP) Declaration error at <location>: UDPs cannot have inout ports
CAUSE: In a user-defined primitive (UDP) declaration at the specified location in a Verilog Design File (.v), you declared an inout
port. However, a UDP can only declare output
and input
ports.
ACTION: Declare the port as an input
or output
, or remove the port from the UDP declaration.