ID:275077 Can't create HDL Design File because LATCH primitive "<name>" is missing signal(s)
CAUSE: You created a
LATCH
primitive is missing input, enable, or output signals. The Quartus Prime software cannot convert a LATCH
primitive without properly connected input, enable, or output signals into a valid group of VHDL or Verilog statements.
ACTION: Make sure the necessary input, enable, and output signals are connected to the LATCH
primitive and create the HDL design file again.