ID:186512 coreclk input port (phase compensation FIFO read clock) of GXB receiver channel <name> with channel width of <number> is sourced by node "<name>". The coreclk input should be fed by the coreclk output of the GXB transmitter PLL that feeds the write clock port of this receiver's phase compensation FIFO
CAUSE: The coreclk
input port (phase compensation FIFO read clock) of the specified GXB transmitter PLL that feeds the write clock port of this receiver's phase compensation FIFO.
ACTION: Modify the design so that the coreclk
input port of the specified GXB receiver channel is fed by the coreclk
output of the GXB transmitter PLL that feeds the write clock port of this receiver's phase compensation FIFO.