ID:186235 Port <name> of enhanced PLL "<name>" cannot feed more than <number> single-ended or <number> differential output pins
CAUSE: The specified external clock port of the specified enhanced PLL drives more than the specified number of single-ended or differential output pins. However, the enhanced PLL must not feed more than the specified number of single-ended or differential output pins.
ACTION: Modify the design so the enhanced PLL feeds no more than the specified number of single-ended or differential output pins.