ID:167085 Atom "<name>" of type "<name>" can only be clocked from one of the following core signals
CAUSE: The PLL's clock input can be driven from multiple refclk
pins, cascaded from one core PLL and one core signal. However, this PLL has more than one core signal driving the clock input.
ACTION: Remove the extra core signals or add a refclk
compatible I/O standard assignments to the pins driving the PLL clock inputs.