ID:15912 Input port <text> and output port <text> of PLL "<name>" are not properly connected.
CAUSE: When the operation_mode
parameter of the specified PLL is set to normal
or source_synchronous
, the fbin
input of the specified PLL must be driven by the fbout
output of the same PLL through a Clock Control Block. If the user does not instantiate the Clock Control Block in the design, the Quartus Prime software inserts a Clock Control Block automatically in the fitter.
ACTION: Make sure the fbin
input and the fbout
output of the specified PLL are connected properly.