ID:18792 WYSIWYG primitive "<lutram name>" and WYSIWYG primitive "<reg name>" are connected to different read and write clock sources. Port Clear is configured as sclear input when connected to a HiPI register must be connected with same clock source.

CAUSE: Port Clear configured as sclear input must be connected to a HiPI register with same read and write clock source.

ACTION: Modify the design to connect clr with a HiPI register to have same read and write clock source.