ID:19188 WYSIWYG primitive "<name>" has clock port <name>[<index>] that is driven by VCC or GND
CAUSE: The specified clock
port of the specified WYSIWYG primitive is driven by VCC
or GND
. When a port is driven by VCC
or GND
, the registers are disabled and the registered signal remains at its current power_up value.
ACTION: If you are bypassing a register driven by the clock port, modify the design so that the CLOCK
parameter for the register is set to NONE
. If you are setting a constant value for the registered signal, modify the design so that the registered signal is set to VCC
or GND
, the register is set to NONE
, and the port must be connected.