ID:14825 Illegal directional connection from the <object> "<name>" to the <object> "<name>"
CAUSE: The directional connection between the specified nodes created a multiple-driver situation at the target node.
For example, this error typically occurs when you have a directional assignment from a bidirectional pin to an other pin that has one or more tri-state drivers.
The following Verilog design illustrates this issue.
module test (input in, oe, inout bidir, output out);
assign out = bidir;
assign out = oe ? in : 1'bZ;
endmodule
In the example, the first continuous assignment creates an illegal directional connection in between bidir
to out
. The assignment implies that data only flows from bidir
to out
. However, the assignment does not indicate a driving condition, so the Quartus Prime software interprets that bidir
always drives the output pin. However, out
also has a tri-state driver. As a result, a potential electrical conflict exists if the tri-state driver for out
is active. ACTION: Remove the directional connection from the design or specify a driving condition.