Perform an RTL Functional Simulation (Verilog)
- To verify that pre-existing libraries are not attached in the
Active-HDL software:
- Click Library Manager window appears. .The
- Browse to <Active-HDL installation directory>/vlib/altera_mf.
- If simulation libraries are present for your version of the Quartus® Prime software, you can skip to step 5. Otherwise you can download the appropriate version library files from the Aldec website or create them manually with steps 2 through 4.
- To create a workspace and compile simulation libraries in the
Active-HDL software:
- Click New Design Wizard appears. . The
- Select Create an Empty Design and keep the Create New Workspace option selected.
- Click Next. The Property page appears. Click .
- Type the name in the Design
name and Library name
fields, for example,
altera_mf_ver
orlpm_ver
. Select the location of your design in the Design folder field, and click Next. Intel recommends to use same name for the design and the library. - Click Finish to complete the wizard.
- Click .
- Browse to < Quartus® Prime installation directory>/eda/sim_lib and add the necessary simulation model files. For example, compile the altera_mf_.v model files into the altera_mf_ver library, and compile the 220model.v model files into the lpm_ver library.
- Select altera_mf.v. to compile all the files and add them to the design library, for example,
- Click .
- Map the created library in the Active-HDL software. To register
simulation libraries:
- Click Library Manager window appears. . The
- Click .
- Locate the .lib file, for example, altera_mf_ver.lib, from the design directory you created in the previous steps, and click Open.
- To create a workspace in the Active-HDL software and compile your
testbench and design files into the work library:
- To add your testbench files in the Active-HDL software, in the Design Browser, click the Top-level Selection list. Select the top-level module, which is your testbench.
- To add the required simulation library in the Active-HDL software, click
Design Settings dialog box appears.
. The
- Expand the Simulation category and click Verilog.
- In the Verilog Libraries window, click the Add library icon and click OK to insert the required Verilog simulation libraries, for example, altera_mf_ver, lpm_ver and altera_ver.
- In the Design Settings dialog box, expand the Simulation category and click Access to Design Objects. Turn on Read (+r) to view waveforms in the Waveform window.
- To initialize simulation in the Active-HDL software, click Design Browser automatically switches to the Structure tab and displays the design tree. . This loads the simulation. The
- To perform the simulation in the Active-HDL software:
- Click .
- Drag signals of interest from the Structure tab of the Design Browser to the Waveform window.
- Click .
- In the pop-up window, specify how long you want your simulation to run, for example, 500 ns.