read_comments_as_HDL VHDL Synthesis Directive
A VHDL synthesis directive that directs Analysis & Synthesis to perform logic synthesis on portions of the design code that are in comments. By commenting out code in the design and using this synthesis directive, you can direct Analysis & Synthesis to perform logic synthesis on code that is specific to logic synthesis, while also ensuring that the code does not affect design simulation.
To use the read_comments_as_HDL
synthesis
directive, you can specify the read_comments_as_HDL
synthesis directive with the on
keyword in a comment
located immediately before the comments you want Analysis &
Synthesis to process, and specify the
read_comments_as_HDL
synthesis directive with the
off
keyword in a comment located immediately after the
comments you want Analysis & Synthesis to process. In the
comment, precede the synthesis directive with the
synthesis
keyword.
For example, in the following code, Analysis & Synthesis
performs logic synthesis on the comment -- GENERIC (LPM_FILE
: string := "UNUSED" );
. Analysis & Synthesis does not
perform logic on any comments after the comment -- synthesis
read_comments_as_HDL off
(unless the user uses the
read_comments_as_HDL
synthesis directive again):
ENTITY asyn_rom_128x7 IS
-- synthesis read_comments_as_HDL on
-- GENERIC (LPM_FILE : STRING := "UNUSED" );
-- synthesis read_comments_as_HDL off