ram_init_file VHDL Synthesis Attribute
A VHDL synthesis attribute that specifies initial contents of an inferred memory block in the form of a Memory Initialization File (.mif) Definition. The attribute takes a string value containing the name of the RAM Initialization File (.rif).
syn_ram_init_file
, which behaves identically to the
ram_init_file
synthesis attribute.
To use the ram_init_file synthesis attribute in a VHDL Design File (.vhd), first declare the synthesis attribute with a string type using an Attribute Declaration. Then use an Attribute Specification to associate the ram_init_file synthesis attribute with a Signal or Variable Declaration that represents an inferred RAM. Specify the synthesis attribute value as the name of the file containing content used to initialize your RAM.
For example, in the following code, the Attribute Declaration
declares the ram_init_file synthesis attribute, and the Attribute
Specification specifies that the inferred RAM mem_t
should be
initialized with the content specified in my_init_file.mif:
type mem_t is array(0 to 255) of unsigned(7 downto 0);
signal ram : mem_t;
attribute ram_init_file : string;
attribute ram_init_file of ram :
signal is "my_init_file.mif";