noprune VHDL Synthesis Attribute
A VHDL synthesis attribute that prevents the
Quartus® Prime
software from removing a register that does not directly or
indirectly feed a top-level output or bidir pin, such as a
fanout-free register. This attribute differs from the preserve
attribute, which only prevents a register from being reduced to a
constant or merged with a duplicate register. Standard synthesis
optimizations remove nodes that do not directly or indirectly feed
a top-level output pin or bidir pin.
You may wish to retain a fanout-free register in many cases. For example, if you are compiling a preliminary design that will eventually include fanout logic for the register. You may also intend to use the register for debugging in the Quartus® Prime Simulator or Signal Tap Logic Analyzer. Finally, you may want to route from the register to a Signal Probe Pin after compilation.
Internally, the
Quartus® Prime software uses the Preserve
Fan-out Free Register Node logic option to implement a
noprune
attribute. Thus, the attribute has the same device support
limitations as the logic option.
syn_noprune
. This synthesis attribute behaves identically to the
noprune
synthesis attribute.
To use the noprune
synthesis attribute in VHDL, you must first declare the attribute
in the local scope or import its declaration from the altera_syn_attributes
package in the altera library. You can then use an attribute
specification to associate the attribute with a signal or variable
that infers a register in your design. For example, in the
following code, the attribute declaration declares the noprune
attribute as a boolean object in the local scope, and the attribute
specification associates the attribute with the signal reg1
:
signal reg1: stdlogic;
attribute noprune: boolean;
attribute noprune of reg1: signal is true;