keep VHDL Synthesis Attribute
A VHDL synthesis attribute that directs Analysis & Synthesis to keep a particular wire intact. You can use this synthesis attribute to keep combinational logic so you can observe the combinational logic during simulation or with the Signal Tap Logic Analyzer.
syn_keep
. This synthesis attribute behaves identically to the
keep
synthesis attribute.
Use an Attribute Declaration and Attribute Specifications to use
the keep
synthesis attribute in a design. You must
associate the keep
synthesis attribute only with
signals, and you must specify the synthesis attribute as true. For
example, in the following code, the Attribute Declaration and
Attribute Specification directs Analysis & Synthesis to not
minimize the keep_wire
signal. The Attribute
Declaration declares the keep
synthesis attribute, and
the Attribute Specification associates the keep
synthesis attribute with the keep_wire
signal and
specifies the synthesis attribute as true:
signal keep_wire : std_logic;
attribute keep: boolean;
attribute keep of keep_wire: signal is true;
You cannot use this synthesis attribute for signals that have no fan-out.