Synthesis

You can turn on or off the following synthesis files for generation:

• Create HDL design files for synthesis—Creates Verilog or VHDL design files, as specified by the developer. Qsys Pro interconnect uses Verilog HDL code.
• Create timing and resource estimates for third-party EDA synthesis tools—Generates a non-functional Verilog Design File (.v) for use by some third-party EDA synthesis tools. Estimates timing and resource usage for your IP component. The generated netlist file name is <your_ip_component>_name.v.
• Create Block Symbol File (.bsf)—You can optionally create a (.bsf) file to use in schematic Block Diagram File (.bdf) designs.
• IP-XACT—creates an IP-XACT representation of your generated system.