To perform a timing simulation with the QuestSim GUI
- If you have not already done so, compile libraries and design files with the QuestaSim software.
- If the design contains device-wide reset or device power-up signals, and if you have not already done so, set up the signals in the Verilog Output File or set up the signals in the VHDL Output File.
- On the Simulate menu, click Simulate. The Simulate dialog box appears.
- If you are simulating a Verilog HDL design, click the
Verilog tab. Under Pulse Options, type
0
in the Error Limit and Rejection Limit boxes. - If you are simulating a VHDL design, to specify the Standard Delay Format Output File (.sdo) Definition:
- Click the SDF tab.
- Click Add.
- In the Add SDF Entry dialog box, click Browse. The Select SDF File dialog box appears.
- In the Files of type list, select All Files (*.*).
- Select the Standard Delay Output File.
- Click Open.
- Click OK.
Note: If you are using a testbench file to provide simulation stimuli to the design, in the Apply to region box, specify the path to the design instance in the testbench, starting from the top-level design file. - Click the Design tab.
- In the Name list, expand the work directory and select the design entity that corresponds to the Standard Delay Output File.
- Click Add.
- Select the top-level Verilog HDL or VHDL Output File or testbench.
- Click Add.
- If you are simulating high-speed circuits (including designs
that use HSSI, LVDS, or PLLs):
- Click the Other tab.
- In the Other options
box, type
+transport_int_delays
and+transport_path_delays.
- Click OK.
- Click Load.
- To direct the QuestaSim software to generate a Value Change Dump File (.vcd) Definition that you can then use to perform
power analysis in the Quartus® Prime PowerPlay Power Analyzer,
type the following command at the QuestaSim prompt:
source<testbench or design instance name>_dump_all_vcd_nodes.tcl
The Tcl Script File (.tcl) Definition directs the QuestaSim software to monitor and write the output signals contained in the Tcl Script File to a Value Change Dump File during simulation.
- Perform the timing simulation in the QuestaSim software.