To setup the simulator environment

  1. (Standard Edition only) On the Tools menu, click Options and then click EDA Tool Options. Specify the path to your simulator executable file.
  2. On the Assignments menu, click Settings.
  3. In the Category list, select Simulation under EDA Tool Settings.
  4. In the Tool name list, select your supported simulator.
  5. If enabled, you can turn on Run gate-level simulation automatically after compilation.
  6. In the Format for output netlist list, select either VHDL or Verilog HDL.
  7. In the Output directory box, type or browse to the location where you want output files saved.
  8. If you want to map illegal HDL characters, turn on Map illegal HDL characters.
  9. To filter glitches from the netlist and any corresponding Standard Delay Format Output File (.sdo) Definition, turn on Enable glitch filtering.
  10. If you want to generate a Value Change Dump File (.vcd) Definition file for power analysis,follow these steps:
    1. Turn on Generate Value Change Dump (VCD) file script.
    2. Under Script settings, specify the type of output signals to include in the .vcd script and the name of the test bench instance for which you are performing the simulation. If you are running your simulation with a test bench selected, the design instance name must be identical to and specified.
  11. To specify less common EDA Netlist Writer options,follow these steps:
    1. Click More EDA Netlist Writer Settings.
    2. Type the desired Architecture name in VHDL output netlist.
    3. To add the devpor, devclrn, and devoe signals as input ports in the top-level design hierarchy in the netlist, turn on Bring out device-wide set/reset signals as ports.
    4. To disable setup and hold violation detection in bi-directional pins, turn on Disable detection of setup and hold violations detection in input registers of bi-directional pins.
    5. To disable writing the entity definition of top-level entity into the VHDL file, turn on Do Not Write Top Level VHDL Entity.
    6. To flatten all buses in the netlist, turn on Flatten buses into individual nodes.
    7. To generate a Verilog Output File (.vo) or VHDL Output File (.vho) for a functional simulation, turn on Generate netlist for functional simulation only.
    8. To maintain the original design hierarchy in the netlist, turn on Maintain hierarchy.
    9. To truncate hierarchical node names to 80 characters or more, turn on Truncate long hierarchy paths.
    10. Click OK.