Turn on Generate Value Change Dump (VCD) file script.
Under Script settings, specify the type of output signals to
include in the .vcd script and the name of the
test bench instance for which you are performing the simulation. If you are running
your simulation with a test bench selected, the design instance name must be identical
to and specified.
To specify less common EDA Netlist Writer options,follow these
steps:
Click More EDA Netlist Writer
Settings.
Type the desired Architecture name in
VHDL output netlist.
To add the devpor, devclrn, and devoe signals
as input ports in the top-level design hierarchy in the netlist, turn on Bring out device-wide set/reset signals as ports.
To disable setup and hold violation detection in bi-directional
pins, turn on Disable detection of setup and hold
violations detection in input registers of bi-directional pins.
To disable writing the entity definition of top-level entity into
the VHDL file, turn on Do Not Write Top Level VHDL
Entity.
To flatten all buses in the netlist, turn on Flatten buses into individual nodes.
To generate a Verilog Output File (.vo) or VHDL Output File (.vho) for
a functional simulation, turn on Generate netlist for
functional simulation only.
To maintain the original design hierarchy in the netlist, turn on
Maintain hierarchy.
To truncate hierarchical node names to 80 characters or more, turn
on Truncate long hierarchy paths.