T8 Delay (DQS to input register) logic option

A logic option that specifies the propagation delay for the T8 delay cell. This is an advanced option; use this option only after compiling your project, checking the I/O timing, and determining that the timing is unsatisfactory. This option is ignored if it is applied to anything other than an input or bidirectional pin.

This option is available for supported device(ArriaIIGZ, StratixIII, StratixIV, and StratixV) families.

Scripting Information

Keyword: t8_delay0

Settings:<integer>

Note:

For more information, refer to the data sheet for the desired device family, which is available from the Literature section of the Altera website.