Auto Packed Registers logic option

A logic option that allows the Compiler to implement a register and a combinational function in the same logic cell, or to implement registers using I/O cells, RAM blocks, or DSP blocks instead of logic cells. This option controls how aggressively the Fitter combines registers with other function blocks in order to reduce logic element count. When using the Auto Packed Registers option, you must turn on the Optimize IOC Register Placement for Timing logic option.

You can use this option as a project-wide option or assign it to a design entity. If the register and the other cell being considered for placement in the same logic cell, I/O cell, DSP block, or RAM block have different settings for the Auto Packed Registers option, the less aggressive of the two settings determines if the Fitter can place the combination together.

This option is available for all Intel devices supported by the Quartus^® Prime software.