Ignore Verilog Initial Constructs logic option

A logic option that instructs Analysis & Synthesis to ignore initial constructs and variable declaration assignments in your Verilog HDL design files. By default, Analysis & Synthesis derives power-up conditions for your design by elaborating these constructs. This option is provided for backward compatibility with previous versions of the Quartus^® Prime software that ignored these constructs by default. Use this option to restore the previous behavior of your design in the current version of the software.

This option is available for all Intel devices.