Synchronization Register Chain Length logic option
A logic option that allows you to specify the retiming behavior for a sequence of synchronization or metastability registers. All registers in the sequence have the same clock and have no fan-out in between, such that the first register is fed by a pin or by logic in another clock domain. These registers are not moved during gate-level retiming. The length of the sequence is specified by a variable.
This option is available for all Intel devices supported by the Quartus® Prime software except MAX3000 and MAX7000 devices.
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Settings:2 | <register value> *default |
Note: For more information about metastability, see
the "Managing Metastability with the Quartus® Prime Software" chapter
in the Quartus® Prime Handbook, volume 1.