Performing a Timing Simulation with the VCS Software

To perform a timing simulation of a Quartus® Prime generated Verilog Output File (.vo) Definition and the corresponding Standard Delay Format Output File (.sdo) Definition with the Synopsys VCS software:

  1. If you have not already done so, perform Setting Up the VCS Working Environment.
  2. To direct the VCS software to generate a Value Change Dump File (.vcd) Definition that you can then use to perform power analysis in the Quartus® Prime PowerPlay Power Analyzer, include the Quartus® Prime-generated Verilog Design File (.v) Definition in the testbench file for the design by adding the following line to the testbench file:
    include<testbench or design instance name>_dump_all_vcd_nodes.v

    The Verilog Design File directs the VCS software to monitor and write the output signals contained in the Verilog Design File to a VCD File during simulation.

  3. Compile the Verilog Output File with the VCS software with one of the following commands typed at the command prompt.

    To generate a simv.exe file, which you can use later to simulate the design:

    vcs <testbench>.v <design name>.vo -v \quartus\eda\sim_lib\<device family>_atoms.v +compsdf

    To compile the Verilog Output File with the VCS software and simulate it automatically:

    vcs -R <testbench>.v <design name>.vo -v \quartus\eda\sim_lib\<device family>_atoms.v +compsdf

The EDA Netlist Writer generates a functional simulation netlist rather than a timing simulation netlist for designs that specify the StratixV or newer device families, even if you specified a timing simulation netlist.

  • If your design contains high-speed elements such as GXB blocks, you must use transport delay options to perform a timing simulation. You can add transport delay options for the VCS software when performing a timing simulation with Standard Delay Format Output File (.sdo) Definition. For more information on using transport delays, see the "Synopsys VCS and VCS-MX Support" chapter in the Quartus® Prime Handbook, vol. 3.

  • Intel recommends that you set Time scale settings to picoseconds (ps) in the interface or with command-line commands when performing timing simulations of designs with RAM.
  • If your design contains the alt2gxb megafunction, refer to the alt2gxb Help topic for required settings information.
Note: For more information about using EDA simulators, refer to Synopsys VCS and VCS MX Support in the Quartus® Prime Handbook.