To prepare for a functional simulation of a Verilog HDL design
with the Synopsys VCS software, you can type a command that
compiles the design and generates a simv.exe file that you
can use to simulate the design. Alternatively, you can type a
command that compiles and simulates the design automatically.
To perform a functional simulation of a Verilog HDL design with
the VCS software from the command line:
-
If you have not already done so, set up the
VCS working environment.
-
Refer to the following table and type the appropriate command at
the command prompt.
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Design Type |
Commands for Compiling the Design and Generating a simv.exe File |
Commands for Compiling and then Automatically Simulating the Design |
Verilog HDL design without HEX File |
vcs <design name>.v [<testbench>.v] -v <library file>.v |
vcs -R <design name>.v [<testbench>.v] -v <library file>.v |
Verilog HDL design with HEX File |
vcs -v \quartus\eda\sim_lib\nopli.v<library file>.v <design name>.v [<testbench>.v] - |
vcs -R -v \quartus\eda\sim_lib\nopli.v <library file>.v <design name>.v [<testbench>.v] - |
-
You must type the above commands for each source file in the design, where the <design name>
.v
and <testbench>
.v
variables may each represent one or more of the source files of the design.
-
The <library file>
.v
variable may represent one or more of the functional simulation libraries.
-
Refer to the VCS User Guide for more information on the required and optional environment variables.
Important: Important: If your design contains the alt2gxb megafunction, refer to the alt2gxb Help topic for required settings information.
-
To continue with the VCS simulation flow, proceed to Performing a Timing Simulation with the VCS Software.
Note: For more information about using EDA simulators, refer to
Synopsys
VCS and VCS MX Support in the Quartus® Prime Handbook.