Performing a Gate-Level Simulation with the Riviera-PRO Software

You can use the Aldec Riviera-PRO software to perform a gate-level (post-fit) simulation of a VHDL or Verilog HDL design that contains Intel-specific components.

Note: The Riviera-PRO software not only has its own native command-line commands, but also supports ModelSim command-line commands. In the following steps, the ModelSim commands are the commands that start with "v", such as vlib.
  1. If you have not already done so, set up the Riviera-PRO working environment.
  2. Perform a full compilation.
  3. To generate gate-level (post-fit) simulation files from the command line, run the Quartus® Prime EDA Netlist Writer by typing the following command:

    For Verilog HDL designs:

    quartus_eda --simulation --tool=rivierapro --format=verilog < design > < project directory >

    For VHDL designs:

    quartus_eda --simulation --tool=rivierapro --format=vhdl < design > < project directory >
    Note: If you already selected the Riviera-PRO software as your simulation tool in a Quartus® Prime project, use the command quartus_eda <design>.
  4. Start the Riviera-PRO simulator in command-line mode from the / <Riviera_PRO root directory> /runvsimsa.bat file (Windows) or the runvsimsa script (Linux).
  5. To create a working library, type the following command: alib/vlib <library name>
  6. To set the value of theworklibvariable, type the following command: set worklib <library name>

    <library name> is typically specified as work.

  7. To map the logical name onto library index, type the following command: amap/vmap <library name>
  8. To compile the Verilog HDL or VHDL simulation library files:
    1. To create a library for the simulation library files, type the following command: alib/vlib <simulation library name>
    2. Choose the Intel post-fit libraries provided with the Quartus® Prime software for your design.
    3. To compile the files chosen in the previous step, type: alog/vlog/acom/vcom -dbg -work <simulation library name> <file name>
      If you do not need to debug your design, you should compile the source files without the-dgbswitch, which can decrease simulation speed.
  9. To compile the Verilog HDL or VHDL design and test bench files, type the following command: alog/vlog/acom/vcom -dbg -work <library name> <file name>
    If you do not need to debug your design, you should compile the source files without the-dgbswitch, which can decrease simulation speed.
  10. To initialize the simulation, type the following command:

    For Verilog HDL designs:

    asim/vsim -t 1ps -L < library1 > -L < library2 > ... <top module>

    For VHDL designs:

    asim/vsim -t 1ps -sdftyp /UUT=< sdo file > -L < library1 > -L < library2 > ... <top module>
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    Switch/Argument

    Description
    -t

    Defines the time scale to be simulated in ps
    -sdftyp

    Specifies that the typical timing values from the Standard Delay Format Output File are used
    <sdo file>

    Specifies the post-fit Standard Delay Format Output File generated by the Quartus® Prime software
    /UUT

    Region argument for the -sdftyp switch
    -L

    Allows you to specify multiple simulation libraries that you have already compiled.
    Note:

    Once you initialize the simulation in this step, the simulation database (.asdb file) is created.

  11. To run the simulation, type the following command: run<running time>

To run the simulation until the end, leave out the <running time> argument.

Note:

Use the command transcript file<file_name> to record messages.

Note: For more information about using EDA simulators, refer to Aldec Active-HDL and Riviera-PRO Support in the Quartus® Prime Handbook.