Advanced Synthesis Settings Dialog Box

Allow Any RAM Size for Recognition

Allows the Compiler to infer RAMs of any size, even if they don't meet the current minimum requirements.

Allow Any ROM Size for Recognition

Allows the Compiler to infer ROMs of any size even if the ROMs do not meet the design's current minimum size requirements.

Allow Any Shift Register Size for Recognition

Allows the Compiler to infer shift registers of any size even if they do not meet the design's current minimum size requirements.

Allow Any Shift Register Merging Across Hierarchies

Allows the Compiler to take shift registers from different hierarchies of the design and put them in the same RAM.

Allow Synchronous Control Signals

Allows the Compiler to utilize synchronous clear and/or synchronous load signals in normal mode logic cells. Turning on this option helps to reduce the total number of logic cells used in the design, but might negatively impact the fitting since synchronous control signals are shared by all the logic cells in a LAB.

Analysis & Synthesis Message Level

Specifies the type of Analysis & Synthesis messages displayed. Low displays only the most important Analysis & Synthesis messages. Medium displays most messages, but hides the detailed messages. High displays all messages.

Auto Carry Chains

Allows the Compiler to create carry chains automatically by inserting CARRY_SUM buffers into the design. The length of the chains is controlled with the Carry Chain Length option. If this option is turned off, CARRY buffers are ignored, but CARRY_SUM buffers are unaffected. The Auto Carry Chains option is ignored if you select Product Term or ROM as the setting for the Technology Mapper option.

Auto Clock Enable Replacement

Allows the Compiler to find logic that feeds a register and move the logic to the register's clock enable input port.

Auto DSP Block Replacement

Allows the Compiler to find a multiply-accumulate function or a multiply-add function that can be replaced with the altmult_accum or the altmult_add IP core.

Auto Gated Clock Conversion

Automatically converts gated clocks to use clock enable pins. Clock gating logic can contain AND, OR, MUX, and NOT gates. Turning on this option may increase memory use and overall run time. You must use the TimeQuest Timing Analyzer for timing analysis, and you must define all base clocks in Synopsys Design Constraints (SDC) format.

Auto Open-Drain Pins

Allows the Compiler to automatically convert a tri-state buffer with a strong low data input into the equivalent open-drain buffer.

Auto RAM Replacement

Allows the Compiler to find a set of registers and logic that can be replaced with the altsyncram or the lpm_ram_dp IP core. Turning on this option may change the functionality of the design.

Auto ROM Replacement

Allows the Compiler to find logic that can be replaced with the altsyncram or the lpm_rom IP core. Turning on this option may change the power-up state of the design.

Auto Resource Sharing

Allows the Compiler to share hardware resources among many similar, but mutually exclusive, operations in your HDL source code. If you enable this option, the Compiler merges compatible addition, subtraction, and multiplication operations. By merging operations, this may reduce the area required by your design. Because resource sharing introduces extra muxing and control logic on each shared resource, it may negatively impact the final f_MAX of your design.

Auto Shift Register Placement

Allows the Compiler to find a group of shift registers of the same length that can be replaced with the altshift_taps IP core. The shift registers must all use the same clock and clock enable signals, must not have any other secondary signals, and must have equally spaced taps that are at least three registers apart.

Automatic Parallel Synthesis

Option to enable/disable automatic parallel synthesis. This option can be used to speed up synthesis compile time by using multiple processors when available.

Block Design Naming

Specify the naming scheme used for the block design. This option is ignored if it is assigned to anything other than a design entity.

Carry Chain Length

Specifies the maximum allowable length of a chain of both user-entered and Compiler-synthesized CARRY_SUM buffers. Carry chains that exceed this length are broken into separate chains.

Clock MUX Protection

Causes the multiplexers in the clock network to be decomposed to 2-to-1 multiplexer trees, and protected from being merged with, or transferred to, other logic. This option helps the TimeQuest Timing Analyzer to understand clock behavior.

Create Debugging Nodes for IP Cores

Make certain nodes (for example, important registers, pins, and state machines) visible for all the IP cores in a design. You can use IP core nodes to effectively debug the IP core, particularly when using the IP core with the SignalTap II Logic Analyzer. The Node Finder, using SignalTap II Logic Analyzer filters, displays all the nodes that Analysis & Synthesis makes visible. When making the debugging nodes visible, Analysis & Synthesis can change the f_MAX and number of logic cells in IP cores.

DSP Block Balancing

Allows you to control the conversion of certain DSP block slices during DSP block balancing.

Disable DSP Negate Inferencing

Allows you to specify whether to use the negate port on an inferred DSP block.

Disable Register Merging Across Hierarchies

Specifies whether registers that are in different hierarchies are allowed to be merged if their inputs are the same.

Extract VHDL State Machines

Allows the Compiler to extract state machines from VHDL Design Files. The Compiler optimizes state machines using special techniques to reduce area and/or improve performance. If set to Off, the Compiler extracts and optimizes state machines in VHDL Design Files as regular logic.

Extract Verilog State Machines

Allows the Compiler to extract state machines from Verilog Design Files. The Compiler optimizes state machines using special techniques to reduce area and/or improve performance. If set to Off, the Compiler extracts and optimizes state machines in Verilog Design Files as regular logic.

Force Use of Synchronous Clear Signals

Forces the Compiler to utilize synchronous clear signals in normal mode logic cells. Turning on this option helps to reduce the total number of logic cells used in the design, but might negatively impact the fitting since synchronous control signals are shared by all the logic cells in a LAB.

HDL Message Level

Specifies the type of HDL messages you want to view, including messages that display processing errors in the HDL source code. Level1 displays only the most important HDL messages. Level2 displays most HDL messages, including warning and information based messages. Level3 displays all HDL messages, including warning and information based messages and alerts about potential design problems or lint errors.

Ignore CARRY Buffers

Ignores CARRY_SUM buffers in the design. This option is ignored if it is applied to anything other than an individual CARRY_SUM buffer or to a design entity containing CARRY_SUM buffers.

Ignore CASCADE Buffers

Ignores CASCADE buffers that are instantiated in the design. This option is ignored if it is applied to anything other than an individual CASCADE buffer or a design entity containing CASCADE buffers.

Ignore GLOBAL Buffers

Ignores GLOBAL buffers that are instantiated in the design. This option is ignored if it is applied to anything other than an individual GLOBAL buffer or a design entity containing GLOBAL buffers.

Ignore LCELL Buffers

Ignores LCELL buffers that are instantiated in the design. This option is ignored if it is applied to anything other than an individual LCELL buffer or a design entity containing LCELL buffers.

Ignore Maximum Fan-Out Assignments

Directs the Compiler to ignore the Maximum Fan-Out Assignments on a node, an entity, or the whole design.

Ignore ROW GLOBAL Buffers

Ignores ROW GLOBAL buffers that are instantiated in the design. This option is ignored if it is applied to anything other than an individual GLOBAL buffer or a design entity containing GLOBAL buffers.

Ignore SOFT Buffers

Ignores SOFT buffers that are instantiated in the design. This option is ignored if it is applied to anything other than an individual SOFT buffer or a design entity containing SOFT buffers.

Ignore Verilog Initial Constructs

Instructs Analysis & Synthesis to ignore initial constructs and variable declaration assignments in your Verilog HDL design files. By default, Analysis & Synthesis derives power-up conditions for your design by elaborating these constructs. This option is provided for backwards compatibility with previous versions of the Quartus^® Prime software that ignored these constructs by default. You can use this option to restore the previous behavior of your design in the current version of the software.

Ignore translate_off and synthesis_off Directives

Instructs Analysis & Synthesis to ignore all translate_off/synthesis_off synthesis directives in your Verilog HDL and VHDL design files. You can use this option to disable these synthesis directives and include previously ignored code during elaboration.

Infer RAMs from Raw Logic

Instructs the Compiler to infer RAM from registers and multiplexers. Some HDL patterns that differ from Altera RAM templates are initially converted into logic. However, these structures function as RAM and, because of that, the Compiler may create an altsyncram IP core instance for them at a later stage when this assignment is on. When this assignment is turned on, the Compiler may use more device RAM resources and fewer LABs.

Iteration Limit for Constant Verilog Loops

Defines the iteration limit for Verilog loops with loop conditions that evaluate to compile-time constants on each loop iteration. This limit exists primarily to identify potential infinite loops before they exhaust memory or trap the software in an actual infinite loop.

Iteration Limit for non-Constant Verilog Loops

Defines the iteration limit for Verilog HDL loops with loop conditions that do not evaluate to compile-time constants on each loop iteration. This limit exists primarily to identify potential infinite loops before they exhaust memory or trap the software in an actual infinite loop.

Limit AHDL integers to 32 Bits

Specifies whether an AHDL-based design should have a limit on integer size of 32 bits. This option is provided for backward compatibility with pre-2000.09 releases of the Quartus software, which do not support integers larger than 32 bits in AHDL.

Maximum DSP Block Usage

Specifies the maximum number of DSP blocks that the DSP block balancer assumes exist in the current device for each partition. This option overrides the usual method of using the maximum number of DSP blocks the current device supports.

This option is useful to set different DSP block usage limits for different partitions.

Maximum Number of LABs

Specifies the maximum number of LABs that Analysis & Synthesis should try to utilize for a device. This option overrides the usual method of using the maximum number of LABs the current device supports, when the value is non-negative and is less than the maximum number of LABs available on the current device.

Maximum Number of M4K/M9K/M20K/M10K Memory Blocks

Specifies the maximum number of M4K, M9K, M20K, or M10K memory blocks that the Compiler may use for a device. This option overrides the usual method of using the maximum number of M4K, M9K, M20K, or M10K memory blocks the current device supports, when the value is non-negative and is less than the maximum number of M4K, M9K, M20K, or M10K memory blocks available on the current device.

Maximum Number of Registers Created from Uninferred RAMs

Specifies the maximum number of registers that Analysis & Synthesis can use for conversion of uninferred RAMs. You can use this option as a project-wide option or on a specific partition by setting the assignment on the instance name of the partition root. The assignment on a partition overrides the global assignment (if any) for that particular partition. This option prevents synthesis from causing long compilations and running out of memory when many registers are used for uninferred RAMs. Instead of continuing the compilation, the Quartus^® Prime software issues an error and exits.

NOT Gate Push-Back

Allows the Compiler to push an inversion (that is, a NOT gate) back through a register and implement it on that register's data input if it is necessary to implement the design. If this option is turned on, a register may power up to an active-high state, so it may need to be explicitly cleared during initial operation of the device. This option is ignored if it is applied to anything other than an individual register or a design entity containing registers. If it is applied to an output pin that is directly fed by a register, it is automatically transferred to that register.

Number of Inverted Registers Reported in Synthesis Report

Specifies the maximum number of inverted registers that the Synthesis Report should display.

Number of Removed Registers Reported in Synthesis Report

Allows you to specify the maximum number of removed registers that the Synthesis Report should display.

Optimization Technique

Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance, minimize logic usage, or balance high performance with minimal logic usage.

Parallel Synthesis

Enables parallel synthesis.

Perform WYSIWYG Primitive Resynthesis

Specifies whether to perform WYSIWYG primitive resynthesis during synthesis. This option uses the setting specified in the Optimization Technique logic option.

Power-Up Don't Care

Causes registers that do not have a Power-Up Level logic option setting to power up with a don't care logic level (X). When the Power-Up Don't Care option is turned on, the Compiler determines when it is beneficial to change the power-up level of a register to minimize the area of the design. A power-up state of zero is maintained unless there is an immediate area advantage.

PowerPlay Power Optimization During Synthesis

Controls the power-driven compilation setting of Analysis & Synthesis. This option determines how aggressively Analysis & Synthesis optimizes the design for power. Off does not perform any power optimizations. Normal compilation performs power optimizations as long as they are not expected to reduce design performance. Extra effort performs additional power optimizations which may reduce design performance.

Remove Duplicate Registers

Removes a register if it is identical to another register. If two registers generate the same logic, the second one is deleted and the first one is made to fan out to the second one's destinations. Also, if the deleted register has different logic option assignments, they are ignored. This option is useful if you wish to prevent the Compiler from removing duplicate registers that you have used deliberately. You can do this by setting the option to Off. This option is ignored if it is applied to anything other than an individual register or a design entity containing registers.

Remove Redundant Logic Cells

Removes redundant LCELL primitives or WYSIWYG primitives. Turning this option on optimizes a circuit for area and speed. This option is ignored if it is applied to anything other than a design entity.

Report Connectivity Checks

Specifies whether the synthesis report should include the panels in the Connectivity Checks folder.

Report Parameter Settings

Specifies whether the synthesis report should include the panels in the Parameter Settings by Entity Instance folder.

Report Source Assignments

Specifies whether the synthesis report should include the panels in the Source Assignments folder.

Resource Aware Inference for Block RAM

Specifies whether RAM, ROM, and shift-register inference should take the design and device resources into account.

Restructure Multiplexers

Reduces the number of logic elements required to implement multiplexers in a design. This option is useful if your design contains buses of fragmented multiplexers. This option repacks multiplexers more efficiently for area, allowing the design to implement multiplexers with a reduced number of logic elements. On minimizes your design area, but may negatively affect design clock speed (f_MAX). Off disables multiplexer restructuring; it does not decrease logic element usage and does not affect design clock speed (f_MAX). Selecting Auto allows the Quartus^® Prime software to determine whether multiplexer restructuring should be enabled. The Quartus^® Prime software uses other synthesis settings, such as the Optimization Technique option, to determine whether multiplexer restructuring should be applied to the design. The Auto setting decreases logic element usage, but may negatively affect design clock speed (f_MAX).

SDC Constraint Protection

Verifies SDC constraints in register merging. This option helps to maintain the validity of SDC constraints through compilation.

Safe State Machine

Directs the Compiler to implement state machines that can recover from an illegal state.

Shift Register Replacement – Allow Asynchronous Clear Signal

Allows the Compiler to find a group of shift registers of the same length that can be replaced with the altshift_taps IP core. The shift registers must all use the same aclr signals, must not have any other secondary signals, and must have equally spaced taps that are at least three registers apart. To use this option, you must turn on the Auto Shift Register Replacement logic option.

State Machine Processing

Specifies the processing style used to compile a state machine. You can use your own User-Encoded style, or select One-Hot, Minimal Bits, Gray, Johnson, Sequential, or Auto (Compiler-selected) encoding.

Strict RAM Replacement

When this option is On, the Compiler is only allowed to replace RAM if the hardware matches the design exactly.

Synchronization Register Chain Length

Specifies the maximum number of registers in a row considered as a synchronization chain. Synchronization chains are sequences of registers with the same clock and no fan-out in between, such that the first register is fed by a pin, or by logic in another clock domain. These registers are considered for metastability analysis (available for some device families), and are also protected from optimizations such as retiming. When gate-level retiming is turned on, these registers are not removed. The default length is set to two.

Synthesis Effort

Controls the synthesis trade-off between compilation speed and performance and area. The default is Auto. You can select Fast for faster compilation speed at the cost of performance and area.

Timing-Driven Synthesis

Allows synthesis to use timing information during synthesis to better optimize the design.