OPERATION_MODE
|
String
|
Yes
|
Specifies the operation of the RAM. Values are
"SINGLE_PORT", "DUAL_PORT",
"BIDIR_DUAL_PORT", or "ROM". If omitted,
the default is "BIDIR_DUAL_PORT".
|
WIDTH_A
|
Integer
|
Yes
|
Specifies the width of the
data_a[] input port. If omitted, the default is
1.
|
WIDTHAD_A
|
Integer
|
Yes
|
Specifies the width of the
address_a[] input port. If omitted, the default is
1.
|
NUMWORDS_A
|
Integer
|
No
|
Number of words stored in memory. If omitted,
the default is 2 ^ WIDTHAD_A.
|
OUTDATA_REG_A
|
String
|
No
|
Specifies the clock for the q_a[]
output port. Values are "CLOCK0",
"CLOCK1", "UNREGISTERED", or
"UNUSED".
If omitted, the default is "UNREGISTERED".
|
ADDRESS_ACLR_A
|
String
|
No
|
Specifies the asynchronous clear for the
address_a[] port. Values are "CLEAR0" and
"NONE". If omitted, the default is "NONE".
|
OUTDATA_ACLR_A
|
String
|
No
|
Specifies the asynchronous clear for the
q_a[] output port. Values are "CLEAR0",
"CLEAR1", "NONE", or
"UNUSED".
If omitted, the default is "NONE".
|
INDATA_ACLR_A
|
String
|
No
|
Specifies the asynchronous clear for the
data_a[] input port. Values are "CLEAR0",
"NONE", or "UNUSED". If omitted, the
default is "NONE".
|
WRCONTROL_ACLR_A
|
String
|
No
|
Specifies the asynchronous clear for the
wren_ainput port. Values are "CLEAR0",
"NONE", or "UNUSED". If omitted, the
default is "NONE". If the value of the RAM_BLOCK_TYPE
parameter is M512 in
SINGLE_PORT
mode, the value must be set to "NONE".
|
BYTEENA_ACLR_A
|
String
|
No
|
Specifies the asynchronous clear for the
byteena_a[] input port. Value is "NONE".
For Cyclone and Stratix devices, a value of "CLEAR0"
is also allowed.
|
WIDTH_BYTEENA_A
|
Integer
|
No
|
Specifies the width of the
byteena_a[] input port. The
WIDTH_BYTEENA_A parameter value must be equal to
WIDTH_A / BYTE_SIZE.
|
WIDTH_B
|
Integer
|
No
|
Specifies the width of the
data_b[] input port. When the
OPERATION_MODE parameter is set to
"DUAL_PORT" mode, the WIDTH_B parameter
is required. If omitted, the default is 1.
|
WIDTHAD_B
|
Integer
|
No
|
Specifies the width of the
address_b[] input port. If omitted, the default is
1.
|
NUMWORDS_B
|
Integer
|
No
|
Number of words stored in memory. If omitted,
the default is 2 ^ WIDTHAD_B.
|
RDCONTROL_REG_B
|
String
|
No
|
Specifies the clock for the
rden_b port during read mode. Values are
"CLOCK0" and "CLOCK1". If omitted, the
default is "CLOCK1".
|
ADDRESS_REG_B
|
String
|
No
|
Specifies the clock for the
address_b[] port. Values are "CLOCK0" and
"CLOCK1". If omitted, the default is "CLOCK1".
Note: Note: ADDRESS_REG_Bserves as the reference for the
clock source of port B if other parameters are not specified or are
different fromADDRESS_REG_B.
|
INDATA_REG_B
|
String
|
No
|
Specifies the clock for the
data_b[] port. Values are "CLOCK0" and
"CLOCK1". If omitted, the default is "CLOCK1".
|
WRCONTROL_WRADDRESS_REG_B
|
String
|
No
|
Specifies the clock for the
wren_b and address_b[] port during write
mode. Values are "CLOCK0" and "CLOCK1".
If omitted, the default is "CLOCK1".
|
BYTEENA_REG_B
|
String
|
No
|
Specifies the clock for the
byteena_b[] port. Values are "CLOCK0" and
"CLOCK1". If omitted, the default is "CLOCK1".
|
OUTDATA_REG_B
|
String
|
No
|
Specifies the clock for the q_b[]
port. Values are "CLOCK0", "CLOCK1", and
"UNREGISTERED". If omitted, the default is
"UNREGISTERED".
|
OUTDATA_ACLR_B
|
String
|
No
|
Specifies the asynchronous clear for the
q_b[] output port. Values are "CLEAR0",
"CLEAR1", and "NONE". If omitted, the
default is "NONE".
Specifies the asynchronous clear parameter for
the output latch in StratixIII devices when the OUTDAT_REG_A
parameter is set to "UNREGISTERED" except in
MLAB mode.
|
RDCONTROL_ACLR_B
|
String
|
No
|
Specifies the asynchronous clear for the
rden_b input
port. Values are "CLEAR0", "CLEAR1",
"NONE", or "UNUSED". The default value is
"NONE".
If the value of the RAM_BLOCK_TYPE
parameter is M512 in
DUAL_PORT mode,
the value must be set to "NONE".
|
INDATA_ACLR_B
|
String
|
No
|
Specifies the asynchronous clear for the
data_b[] input port. Values are "CLEAR0",
"NONE", or "UNUSED". If omitted, the
default is "NONE".
|
WRCONTROL_ACLR_B
|
String
|
No
|
Specifies the asynchronous clear for the
wren_binput port. Values are "CLEAR0",
"NONE", or "UNUSED". If omitted, the
default is "NONE".
|
ADDRESS_ACLR_B
|
String
|
No
|
Specifies the asynchronous clear for the
address_b[] port. Values are "CLEAR0" and
"NONE". If omitted, the default is "NONE".
For
StratixIII devices inBIDIR_DUAL_PORTmode, the
value must be to"NONE".
|
BYTEENA_ACLR_B
|
String
|
No
|
Specifies asynchronous clear for the
byteena_b[] input port. Values are
"CLEAR0", "CLEAR1", "NONE",
or "UNUSED". If omitted, the default is "NONE".
|
WIDTH_BYTEENA_B
|
Integer
|
No
|
Specifies the width of the
byteena_b input port. The WIDTH_BYTEENA_B
parameter value must be equal to WIDTH_B /
BYTE_SIZE.
|
BYTE_SIZE
|
Integer
|
No
|
Specifies the byte size for the byte-enable
mode. Values are:
Note:
|
Device Family
|
Byte Size
|
|
StratixIII (MLAB)
|
5, 8, 9, 10
|
|
StratixIII (BRAM)
|
8, 9
|
|
READ_DURING_WRITE_MODE_MIXED_PORTS
|
String
|
No
|
Specifies the behavior when the read and write
operations occur at different ports on the same RAM address. Values
are "OLD_DATA", "NEW_DATA", and
"DONT_CARE". The default value is
"DONT_CARE". Values of "NEW_DATA"
and "OLD_DATA"
are supported only if read address and output data use write clock
in MLAB mode.
A value of "OLD_DATA"
is not available when the error correction code (ECC) feature is
used in an M-RAM block.
Compatible parameter values:
text-align:left;
|
READ_DURING_WRITE_MODE_ MIXED_PORTS
|
RAM_BLOCK_TYPE
|
|
OLD_DATA
|
M512,M4K,M9K,M144K
|
|
DONT_CARE
|
M-RAM,M9K,M144K
|
|
Automatically selected
|
AUTO
|
|
RAM_BLOCK_TYPE
|
String
|
No
|
Specifies the RAM block type. Values are
device family-dependent. Values are "M-RAM",
"M4K", "M512K", "M9K",
"M144K", "MLAB",
and "AUTO". If omitted, the default is
"AUTO".
|
INIT_FILE
|
String
|
No
|
Name of the Memory Initialization File (.mif) Definition or Hexadecimal (Intel-Format) Output File (.hexout) Definition containing RAM initialization data
("<file name>"), or
"UNUSED". The default is "UNUSED". The
INIT_FILE parameter is unavailable when the
RAM_BLOCK_TYPE parameter is set to M-RAM.
When the OPERATION_MODE parameter is set to
"DUAL_PORT", the Compiler uses only the
WIDTH_B parameters to read the initialization
file.
|
INIT_FILE_LAYOUT
|
String
|
No
|
Specifies the layout port used with the
initialization file. Values are "PORT_A",
"PORT_B", and "UNUSED". If
omitted, the default is "UNUSED". If
the OPERATION_MODE is set to "DUAL_PORT"
mode, the default value is "PORT_B". If the
OPERATION_MODE is set to other modes, the default
value is "PORT_A".
|
MAXIMUM_DEPTH
|
Integer
|
No
|
Specifies the maximum segmented value of the
RAM. The MAXIMUM_DEPTH parameter value depends on the
RAM_BLOCK_TYPE parameter. If omitted, the default is
0.
As the RAM is sliced shallower, the dynamic
power usage decreases. For a 128 deep RAM block, the power used by
the extra LEs starts to outweigh the power gain achieved by
shallower slices. The power usage and RAM/LE usage depends on the
RAM configuration, parameter/port usage, and input vectors.
|
CLOCK_ENABLE_INPUT_A
|
String
|
No
|
Specifies the clock enable for all port
A
inputs. This parameter is available for Stratix III devices
only.
|
READ_DURING_WRITE_MODE_PORT_A
|
String
|
No
|
Specifies the read during write mode for port
A.
Values are "NEW_DATA_NO_NBE_READ",
"NEW_DATA_WITH_NBE_READ"and "OLD_DATA".
If omitted, the default is "NEW_DATA_NO_NBE_READ".
For older devices, the available value is "NEW_DATA_WITH_NBE_READ"
only. In MLAB mode, the
value is "DONT_CARE".
|
READ_DURING_WRITE_MODE_PORT_B
|
String
|
No
|
Specifies the read during write mode for port
B.
Values are "NEW_DATA_NO_NBE_READ",
"NEW_DATA_WITH_NBE_READ" and "OLD_DATA".
If omitted, the default is NEW_DATA_NO_NBE_READ. For
older devices, the only available value is "NEW_DATA_WITH_NBE_READ".
|
ENABLE_ECC
|
String
|
No
|
Specifies whether the ECC feature is on or
off. Values are "TRUE" and "FALSE". For
the ENABLE_ECC
value to be "TRUE",
the value of RAM_BLOCK_TYPE
must be "M144K".
|
POWER_UP_UNINITIALIZED
|
String
|
No
|
Specifies whether to initialize memory
content data to XX..X on power-up simulation. Values are
"TRUE" and
"FALSE". For
M-RAM, the only valid value is TRUE. If
omitted, the default is "FALSE".
|
IMPLEMENT_IN_LES
|
String
|
No
|
Specifies the usage of RAM blocks.
Values are "ON" and
"OFF". Set the
value to "ON" to
implement the RAM in logic cells. If omitted, the default is
"OFF".
|