Create Verilog Instantiation Template Files for Current File Command (File Menu)

You access this command by pointing to Create/Update on the File menu, and then clicking Create Verilog Instantiation Template Files for Current File.

Creates Verilog Design File (.v) Definition that contain the template that is used to instantiate an instance in a Verilog design file. The template file generated represents the instance of the Verilog entities in the current Text Design File (.tdf) Definition VHDL Design File (.vhd) Definition Verilog Design File (.v) DefinitionBlock Design File (.bdf) DefinitionCusp Design File (.cpp), or DSP Builder File (.mdl). The Quartus^® Prime software creates a .v file with the same name for each declared entity in the current file.