Categories, Severity Levels, and Rule IDs for Design Assistant Rules

Specifies which of the following rules you want the Design Assistant to apply when analyzing and generating messages for a design that targets any Altera device supported by the Quartus^® Prime Standard Edition software.

The letter in each Rule ID corresponds to the group of rules based on the following scheme:

A— Nonsynchronous design structure rules
C— Clock rules
R— Reset rules
S— Signal race rules
T— Timing closure rules
D— Asynchronous clock domain rules
M— Finite state machine rules

Rule	Category	Severity Level	Rule ID
Design should not contain combinational loops	Non-synchronous design structure	Critical	A101
Register output should not drive its own control signal directly or through combinational logic	Non-synchronous design structure	Critical	A102
Design should not contain delay chains	Non-synchronous design structure	High	A103
Design should not contain ripple clock structures	Non-synchronous design structure	Medium	A104
Pulses should not be implemented asynchronously	Non-synchronous design structure	Critical	A105
Multiple pulses should not be generated in design	Non-synchronous design structure	Critical	A106
Design should not contain SR latches	Non-synchronous design structure	High	A107
Design should not contain latches	Non-synchronous design structure	High	A108
Gated clock should be implemented according to Altera standard scheme	Clock	Critical	C101
Logic cell should not be used to generate inverted clock	Clock	High	C102
Gated clock is not feeding at least a pre-defined number of clock ports to effectively save power	Clock	High	C103
Clock signal source should drive only input clock ports	Clock	Medium	C104
Clock signal should be a global signal	Clock	High	C105
Clock signal source should not drive registers that are triggered by different clock edges	Clock	High	C106
Combinational logic used as reset signal should be synchronized	Reset	High	R101
External reset should be synchronized using two cascaded registers	Reset	Medium	R102
External reset should be correctly synchronized	Reset	High	R103
Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be correctly synchronized	Reset	High	R104
Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be synchronized	Reset	Medium	R105
Output enable and input of same tri-state node should not be driven by same signal source	Signal race	High	S101
Synchronous port and asynchronous port of same register should not be driven by same signal source	Signal race	High	S102
More than one asynchronous signal source of the same register should not be driven by the same source	Signal race	High	S103
Clock port and any other signal port of the same register should not be driven by the same source	Signal race	High	S104
Nodes with more than specified number of fan-outs: `<n>`	Timing Closure	Information Only	T101
Top nodes with highest fan-out: `<n>`	Timing Closure	Information Only	T102
Data bits are not synchronized when transferred between asynchronous clock domains	Asynchronous clock domains	High	D101
Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain	Asynchronous clock domains	Medium	D102
Data bits are not correctly synchronized when transferred between asynchronous clock domains	Asynchronous clock domains	High	D103

The Design Assistant Settings report lists all the Design Assistant rules, and indicates which rules you turned on.