The same signal source should not drive the synchronous port and any other asynchronous port of the same register, for example aload, adata, preset, and clear (active high and active low). A signal race problem can occur if the synchronous port and the asynchronous port of the same register are driven by the same signal source. The following image shows an example of the same signal source driving the synchronous port and the preset port of the same register:
The Design Assistant does not report a violation if the signal source is from a negative-edge sensitive register of the same clock, and if the source register is directly feeding the D and the clrn port.
Important: Important: This rule can be
turned on or off as a global setting for
the entire design on the Design Assistant
page; or enabled or disabled for nodes, entities, or instances with
Rule S102. This rule has a
High severity level.