In a design, the data bits that are transferred between asynchronous clock domains are synchronized incorrectly, which can result in metastability. The synchronization of the data bits should follow the following guidelines:
- The cascading register synchronization should be triggered on the same clock edge.
- There should be no logic between the output of the transmitting clock domain and the cascaded register synchronization in the receiving asynchronous clock domain.
This rule is applied when the data bits across asynchronous clock domains are synchronized, but fail to adhere to the aforementioned guidelines.
The following image shows an example of the incorrect transfer of all data bits between asynchronous clock domains. The cascading register synchronization is triggered on different clock edges. When the cascaded synchronization registers are triggered on different clock edges, the risk is higher that the second register will not have enough time to resolve the metastable output from the first register.
The following image shows an example of the incorrect transfer of all data bits between asynchronous clock domains. The logic is inserted between the output of the transmitting clock domain and the cascaded synchronization registers in the receiving asynchronous clock domain. The synchronizer may sample unintended data due to glitches generated by the combinational logic. In addition, the extra toggling on the output of the combinatorial logic also increases the risk of metastability.
