Multiple Data Bits That are Transferred Across Asynchronous Clock Domains are Synchronized But Not All Bits May Be Aligned in the Receiving Clock Domain (Design Assistant Rule)

In a design, all of the data bits that belong to multiple-bit data and that are transferred between asynchronous clock domains are synchronized. However, not all data bits may be aligned in the receiving clock domain. Propagation delays may cause skew when the data reaches the receiving clock domain.

The following image shows an example of synchronized data bits that belong to multiple-bit data and that are transferred between asynchronous clock domains:

If the data bits belong to multiple-bit data and a handshake protocol is used, only the data bits that act as REQ (Request) and/or ACK (Acknowledge) signals for the transfer should be synchronized with two or more cascading registers in the receiving asynchronous clock domain.

A violation is also reported if a bus transmits partial data bits across a clock domain.