Reset Signal That is Generated in One Clock Domain and Used in Other, Asynchronous Clock Domains Should be Synchronized (Design Assistant Rule)

In a design, a reset signal that is generated in one clock domain, and used in one or more other asynchronous clock domains, should be synchronized. A reset signal that is not synchronized can cause metastability problems.

The following image shows an example of a reset signal that is generated in one clock domain, and used in one or more other asynchronous clock domains, that is not synchronized:





The synchronization of the reset signal should follow the following guidelines:

The following image shows an example of a synchronized reset signal:





Synchronizing the reset signal delays the signal by an extra clock cycle; this delay should be considered when using the reset signal in a design.

Important: Important: This rule can be turned on or off as a global setting for the entire design on the Design Assistant page; or enabled or disabled for nodes, entities, or instances with Rule R105. This rule has a Medium severity level.