Combinational logic that is used as a reset signal should be synchronized in a design (that is, the combinational logic should drive a register before driving one or more input reset ports of other registers). The following image shows an example of combinational logic that is used as a reset signal:
Glitches in unsynchronized combinational logic that is used as a reset signal can cause the unintentional resetting of the logic's destination register(s). Synchronizing the combinational logic that is used as a reset signal delays the resulting reset signal by an extra clock cycle; this delay should be considered when using the reset signal in a design.
The following image shows an example of synchronized combinational logic that is used as a reset signal:
Rule: R101 Combinational logic used as a reset signal should be synchronized does not report a violation if the combinational logic used is either a 2-input AND or NOR that feeds an active low reset port, or a 2-input OR or NAND that feeds an active high reset port.