An inverter that drives the input clock port of a register in a design, and therefore allows you to use the negative edge of the clock for the register, should not be implemented with a logic cell. The following image shows an example of an inverter implemented with a logic cell:
Implementing the inverter with a logic cell can lead to clock insertion delay and skew, which can cause problems with the timing closure of the design. In addition, for all Altera devices supported by the Quartus® Prime Standard Edition software, using the logic cell is unnecessary because register clocks in the devices have programmable inverts for implementing inverters. The inverter should be implemented with a register clock's programmable invert.
Important: Important: This rule can be
turned on or off as a global setting for
the entire design on the Design Assistant
page; or enabled or disabled for nodes, entities, or instances with
Rule C102. This rule has a
High severity level.