In a design, you can use combinational logic as a clock signal that can prevent certain logic in a circuit from being activated by the clock signal and can therefore reduce the total power consumption of a device. The combinational logic that is used as a clock signal should follow the following guidelines:
- The gating logic should be a two-input AND gate or a two-input OR gate.
- There should be only one input pin that acts as a primary input clock signal to the AND or gate.
- The non-clock input clock enable signal to the AND or OR gate should be synchronized with a register. The register should be clocked by the same input pin that acts as the primary input clock signal to the AND or OR gate.
- If the combinational logic uses an AND gate, the
clock port of the register that drives the AND gate
should be active on the falling edge and the clock port of the
register driven by the AND gate should be active on
the rising edge.
or
If the combinational logic uses an OR gate, the clock port of the register that drives the OR gate should be active on the rising edge and the clock port of the register driven by the OR gate should be active on the falling edge.
- To reduce the probability of glitches, the AND gate should be placed close to the flipflop that generates the gating signal.
- When specifying timing constraints, Altera recommends enclosing the gating circuitry (AND gate and flipflop) in a module. This allows you to specify timing constraints at the module output.
The following image shows an example of combinational logic used as a clock signal, where the gating logic is a two-input AND gate:
The following image shows an example of combinational logic used as a clock signal, where the gating logic is a two-input OR gate:
