You access this tab in the Qsys Component Editor by clicking the
Parameters tab.
In a non-HDL based flow (when you do not have your own HDL file), the
Parameters tab allows you to add Verilog HDL and VHDL
parameters to your component. The following settings affect the parameterization GUI
that Qsys creates for your component in a Qsys system:
-
Parameters
table—Allows you to view and specify the
Verilog HDL parameters or VHDL generics for each interface as
follows:
-
Name—Specifies a
unique name for your parameter.
-
Default
value—Specifies the default value of the
parameter displayed in the GUI.
-
Editable—Turning on
this option enables user editing of the parameter in the GUI.
-
Type—Specifies the
type of parameter as string,
integer, boolean, std_logic, logic vector, natural, or
positive.
-
Group—Specifies the
parameter group name.
-
Tooltip—Specifies
the tooltip text that is displayed in the GUI.
-
Parameter buttons—Allow you to perform the following
functions:
-
Add Parameter—Creates a default
new_parameter in the Parameters table.
-
Remove Parameter—Deletes selected parameter in the Parameters
table.
-
Preview the GUI—Displays the current state of the generated
GUI.
Note: When you have already created an HDL file, you must include the parameters in the
top-level HDL file in order for the parameters to appear in the
Parameters table.