Debug Tools Setting Summary Reports

Reports the following information about all the SignalTap II instances created based on the SignalTapII Logic Analyzer settings selected in the SignalTapII Logic Analyzer Settings page. This report is created during Analysis & Synthesis.

• Instance Index shows the order assigned to the instance by the Quartus^® Prime Standard Edition software.
• Instance Name shows the name of the instance you specify.
• Trigger Input Width shows the width of the node, in bits, that connects to the triggering logic.
• Data Input Width shows the width of the node, in bits, that connects to the acquisition memory.
• Sample Depth shows the number of samples that can be acquired.
• Segments shows the number of segments being analyzed.
• Trigger Flow Control shows the type of trigger flow control in use.
• Trigger Conditions shows the number of sequential trigger condition levels.
• Advanced Trigger Conditions shows the number of advanced trigger condition levels set among all trigger levels.
• Trigger In Used shows whether the trigger-in setting is turned on or off.
• Trigger Out Used shows whether the trigger-out setting is turned on or off.
• Power-Up Trigger Enabled shows whether the power-up trigger is turned on or off.

Reports information about instances instantiated in a design with the sld_signaltap megafunction. This report is created during Analysis & Synthesis.

• Instance Index shows the order assigned to the instance by the Quartus^® Prime Standard Edition software.
• Instance Name shows the name of the instance as modified by the user.
• Trigger Input Width shows the width of the acq_trigger_in, in bits, that connects to the triggering logic.
• Data Input Width shows the width of the acq_data_in, in bits, that connects to the acquisition memory.
• Sample Depth shows the number of samples that can be acquired.
• Trigger Levels shows the number of sequential trigger condition levels.
• Advanced Trigger Levels shows the number of advanced trigger condition levels in a series you set for sampling.
• Trigger In Used shows whether the trigger_in is connected.
• Trigger Out Used shows whether the trigger_out is connected.
• Hierarchy Location shows the hierarchy level in which the sld_sinaltap megafunction is instantiated.

Reports information about the size of the RAM block, where it is located, and whether you can write to it at run-time. The information is generated during Analysis & Synthesis. You can use the In-System Memory Content Editor by using the IP Catalog to set up and instantiate lpm_rom , lpm_ram_dq , altsyncram , and lpm_constant megafunctions, or by instantiating these megafunctions directly in the design, using the lpm_hint megafunction parameter.

• Instance Index shows the order assigned to the instance by the Quartus^® Prime Standard Edition software.
• Instance ID shows the user-specified ID of the memory block instance.
• Width shows the width of the memory word in bits.
• Depth shows the number of memory words for the memory block instance.
• Mode shows whether the mode is either read/write or read-only, which is determined by the RAM block type.
• Hierarchy location shows the location in the design where the megafunction is instantiated.

Reports the results of performing a compilation with the Logic Analyzer Interface enabled.

• Instance Index shows the order assigned to the instance by the Quartus^® Prime Standard Edition software.
• Instance Name shows the name of the instance.
• Bank Count shows the number of banks that can be connected to the output pins.
• Pin Count shows the number of output pins created to be probed using an external logic analyzer.
• Output/Capture Mode shows whether the output pins are configured in either Registered/State or Combinational/Timing mode.
• Power-up State shows whether the output pins are tri-stated or connected to bank 0 after the Altera device is configured.

Reports the following information about instances of the sld_virtual_jtag megafunction present in the design:

• Instance Indexshows the order assigned to the instance by the Quartus^® Prime Standard Edition software.
• Auto Indexshows whether the Auto Index feature is enabled.
• Index Reassigned shows whether the index was reassigned by the Quartus^® Prime Standard Editionsoftware due to a conflict in the design.
• Address shows the instance address.
• USER1 DR length shows the length of the data register targeting the USR1 JTAG instruction for the instance.
• VIR capture instruction shows the virtual instruction register capture instruction value for the instance.
• IR Width shows the width of the instruction register in bits.
• Hierarchy Locationshows the hierarchy level in which the sld_virtual_jtag megafunction is instantiated.